D-Wave published a peer-reviewed paper in Nature on August 6, 2026, titled "An entangling gate for dual-rail erasure qubits," led by Chief Scientist Robert Schoelkopf alongside Chief Development Officer Trevor Lanting and CEO Alan Baratz. The result itself is a two-qubit entangling gate for superconducting dual-rail cavity qubits. The more consequential fact is what kind of hardware it is built on: not the quantum annealing systems D-Wave has sold commercially for over a decade, but a gate-model architecture aimed squarely at fault-tolerant computation.
What a dual-rail erasure qubit changes
Most superconducting qubit errors show up as bit-flips or phase-flips at unknown times and unknown locations, which is what makes standard quantum error correction expensive: the decoder has to find the error before fixing it. A dual-rail erasure qubit is built so that when a photon is lost, the dominant failure mode in this architecture, the loss converts into a detectable erasure error at a known location in space and time, rather than a silent, unlocated bit-flip. Knowing where and when an error happened is a fundamentally easier correction problem than inferring it, which is the engineering bet behind this qubit type, independent of who is building it.
The numbers behind the claim
The published gate runs in about 500 nanoseconds with an overall fidelity near 99.9%, an erasure rate around 0.5% per gate, and post-selected residual Pauli errors below 0.1%. D-Wave also reports bit-flip error suppression down to the 10⁻⁶ level and an error-reduction factor of roughly 10 per increment of code distance. That last figure is the one worth watching independently of the rest: a 10x reduction per code-distance step, if it holds as the system scales, is the kind of favorable scaling that makes a fault-tolerant roadmap plausible rather than aspirational. It is also, so far, a result from one paper, not yet reproduced by an outside group.
The roadmap attached to it
D-Wave laid out specific, dated intermediate systems: a 17-physical-qubit DR17 system in 2026 with roughly 2x logical error reduction, a 49-qubit DR49 system in 2027 at roughly 20x, a 181-qubit DR181 system in 2028 targeting roughly 2,000x error suppression, a 10-logical-qubit system by 2030, and a 100-logical-qubit system by 2032 capable of over a million logical operations for quantum chemistry, materials science, and quantum AI workloads. Naming specific qubit counts and error-suppression targets per year, rather than a single distant milestone, gives outside observers something concrete to check the company against as each date arrives, which is more than most fault-tolerance roadmaps offer.
Why this matters coming from D-Wave specifically
D-Wave's entire commercial identity, and the bookings growth covered in our top companies ranking, rests on quantum annealing: optimization problems solved through an entirely different physical mechanism than the universal gate-model computation this dual-rail work targets. A Nature paper on a gate-model qubit architecture is D-Wave placing a second, structurally different bet alongside its annealing business rather than doubling down on it, similar in spirit to how IonQ diversified into silicon photonics manufacturing through its SkyWater acquisition. It is a hedge against the possibility that annealing alone does not reach the fault-tolerant, general-purpose computation that chemistry and materials science applications eventually need.
What is still unverified
The fidelity, erasure-rate, and error-suppression numbers are D-Wave's own reported results from its own paper, peer-reviewed but not yet reproduced by an independent lab, the same caveat that applies to most vendor-reported hardware milestones covered on this site. The 2032 roadmap is a target, not a result, and D-Wave's own 2026-2028 intermediate milestones are the nearest, most checkable test of whether the scaling trend in the Nature paper holds up as physical qubit count grows.
What to watch next
DR17, the first named milestone, is dated for this year. Whether D-Wave ships it on schedule, and whether the reported error reduction lands near the claimed 2x, is the first real checkpoint against this roadmap, well before the 2032 target is close enough to matter.