IonQ researchers Min Ye, Andrii Maksymov, and Nicolas Delfosse posted a preprint on August 25, 2026 describing an end-to-end real-time decoding stack for the company's proposed Walking Cat trapped-ion fault-tolerant architecture. The paper reports that the entire pipeline runs on a single conventional CPU and keeps decoding overhead low enough that a 408-logical-qubit workload with more than one million T gates does not stall the quantum side.
The numbers below come from the arXiv preprint and from IonQ's own LinkedIn summary. They are architecture simulations and vendor-reported estimates, not an independent hardware demonstration.
What the decoder has to do
Real-time decoding is the classical computing step that turns raw syndrome measurements into corrections during a fault-tolerant computation. If the decoder falls behind the syndrome stream, conditional operations downstream have to wait, the backlog grows, and the whole computation slows down or fails. Our earlier post on the real-time decoding bottleneck explains why this is a hard throughput problem rather than a simple latency target.
Most published decoder work focuses on a memory experiment or a small number of logical operations. IonQ's claim is larger: an end-to-end stack that handles detector error model generation, decoding of all logical qubits, logical operations, and magic-state factories, all in one pipeline.
The reported benchmarks
The authors benchmark the decoder on workloads up to 408 logical qubits and one million T gates. For a trapped-ion architecture with a 1 to 5 millisecond QEC cycle time, the paper reports that decoding stretches total execution time by less than 0.3% at a CNOT error rate of 10⁻⁴, and by less than 12% at a CNOT error rate of 5 × 10⁻⁴, across every workload studied.
IonQ's own social summary narrows that further, claiming a computational stretch as low as 0.03% on the 408-logical-qubit workload when running on a single off-the-shelf Apple M4 Max CPU.
Why it matters if it holds up
If a single CPU decodes a full MegaQuOp-class workload in real time, classical decoding is unlikely to be the bottleneck for IonQ's proposed architecture. That is a meaningful architectural claim, because other fault-tolerance roadmaps rely on FPGAs, ASICs, or large multicore servers to keep pace with the syndrome stream.
The result also fits the broader argument IonQ has been making: that its trapped-ion cycle times, measured in milliseconds rather than microseconds, give classical decoding more time per round and make CPU-based decoding practical in a way it is not for superconducting platforms.
What is still a simulation
The paper is a simulation of a proposed architecture, not a measurement of a working fault-tolerant machine. The Walking Cat design itself remains a blueprint. The error rates, cycle times, and qubit counts are assumptions or targets, not demonstrated hardware specifications. The 0.03% stretch figure is IonQ's own summary figure, not an independently reproduced benchmark.
The direction is worth tracking. Real-time decoding at the MegaQuOp scale is a real milestone on paper. The next check is whether the hardware that is supposed to feed this decoder hits the same error rates and speeds the simulation assumes.
Read the preprint on arXiv for the full decoder description and benchmarks. For context on why decoding matters for fault-tolerant quantum computing, see our logical qubits explainer and the decoding bottleneck post.