A new arXiv preprint proposes RushHour, a dynamic architecture and compiler for lattice surgery in fault-tolerant quantum computers. The system changes logical-qubit layouts, ancilla space, and resource-state allocation during program execution instead of fixing every location before execution.
The authors evaluated RushHour against six existing compilers across 35 benchmark circuits. On the smallest modeled chips, 86 percent of benchmarks ran with RushHour while every comparison design required a chip 1.2 to 3.5 times larger. On space-constrained chips, RushHour reached a successful shot between 2.0 and 7.2 times sooner than the best feasible alternative, measured by the paper's median results.
These figures come from compiler simulations, not a physical quantum processor. The result addresses a major fault-tolerance scheduling problem, but hardware experiments still need to confirm the assumed layout, movement, and timing model.
Why lattice surgery needs space management
Surface-code quantum computers store logical qubits in patches of physical qubits. Lattice surgery performs logical operations by merging and separating neighboring patches. Large algorithms also need routing space, temporary ancilla patches, and magic states for non-Clifford gates.
Static compilers reserve those resources before execution. A circuit might need a large area for one part of a computation and more parallelism during another part. Fixed layouts force one compromise across the full program.
RushHour treats the lattice layout as a changing machine state. The system moves ancilla space, allocates resource states when operations need them, and rotates logical-qubit patches during execution. A dedicated Lattice Management Unit handles reconfiguration, while the RushHour Compiler schedules operations and movement together.
What the benchmark reported
The evaluation used 35 Clifford plus T circuits from FTCircuitBench and MQT Bench. The circuits ranged from 12 to 100 logical qubits and included workloads with up to 186,000 T gates. The authors ran compilations on a 384-core server with a one-hour limit and four gigabytes of memory per circuit.
At RushHour's minimum feasible chip size, 30 of 35 benchmarks ran where every baseline failed. Across the full benchmark set, the comparison designs needed 1.2 to 3.5 times more physical space for their smallest feasible chips.
The timing result followed the same pattern. On tight chips, RushHour reached a successful shot up to a median 7.2 times sooner than the best feasible baseline. At twice the physical minimum, RushHour produced the best result on 89 percent of benchmarks.
Why this matters for early fault tolerance
Early fault-tolerant machines will have limited physical-qubit budgets. A compiler that reduces the minimum chip size gives hardware designers more room to run useful circuits before full-scale systems arrive.
The result also exposes a space-time tradeoff. A design with more physical qubits might finish sooner. A compact design might finish later but fit inside available hardware. RushHour uses one dynamic execution model across this tradeoff instead of requiring separate static layouts for separate chip sizes.
This connects directly to logical qubits and fault tolerance. Error correction does not remove resource constraints. Logical operations still need physical patches, routing paths, measurements, decoding, and temporary states. Compiler decisions determine how much hardware each algorithm needs.
What still needs testing
RushHour's results depend on a modeled machine with specific assumptions about lattice movement, reconfiguration latency, reaction time, physical error rates, and resource-state production. The paper evaluates those assumptions in simulation. No QPU executed the benchmark circuits.
The next test is hardware-backed compilation with measured movement and control costs. Independent teams also need to reproduce the results across different code distances, noise models, circuit families, and hardware layouts.
RushHour does not add physical qubits. It changes how a fault-tolerant machine schedules and reuses them. If hardware supports the required reconfiguration speed, dynamic lattice surgery offers a path to running larger logical circuits on early systems with less physical space.