A team from the University of Science and Technology of China and Origin Quantum Computing published a new family of quantum error-correcting codes on July 22, 2026, called routing codes. The headline number: weight-7 routing codes cut physical-qubit overhead by roughly a factor of 8 compared to surface codes at a similar logical error rate, in circuit-level simulation. That "in simulation" qualifier matters, and we'll come back to it.
What routing codes change
Surface codes, the workhorse of most current error-correction roadmaps, need only nearest-neighbor qubit connections, which is easy to build in hardware but expensive in physical-qubit count. The qLDPC family trades that simplicity for efficiency: qLDPC codes need far fewer physical qubits per logical qubit, but historically at the cost of long-range, non-local connections between qubits that are difficult to fabricate on real chips.
Routing codes target that exact trade-off. According to the team, the construction reduces required qubit connectivity and shortens the non-local couplings a qLDPC code otherwise demands, while also enabling parallel data transfer across the chip. That combination is what lets the design apply to both superconducting and neutral-atom platforms, two modalities with different physical connectivity constraints, without needing a bespoke code for each.
The number, and what it's a number of
The 8x overhead reduction comes from comparing weight-7 routing codes against surface codes at a matched logical error rate, using circuit-level noise simulations rather than a physical device. That's the standard, appropriate way to evaluate a new code family before hardware exists to test it on, and it's the same category of result as QuEra's 2:1 physical-to-logical ratio work covered elsewhere on this site: a real, checkable theoretical contribution, not yet a measured result from a working machine.
What to watch next
The test that matters is whether a hardware team, superconducting or neutral-atom, fabricates a routing-code-based logical qubit and reports a real logical error rate, not a simulated one. Our real-time decoding bottleneck piece covers the other half of the fault-tolerance cost equation these overhead numbers feed into: a cheaper code still needs a decoder that keeps up with it in real time. Until a physical demonstration lands, treat the 8x figure as a credible simulation result worth tracking, not yet a hardware milestone.