HRL Laboratories published a result in Nature on July 29, 2026, describing an 18-qubit silicon quantum processor that runs its own control electronics from inside the cryostat, rather than being driven by racks of room-temperature instruments wired in from outside. The chip is small by the standards of superconducting or trapped-ion systems chasing hundreds of qubits, but the part worth reading closely is not the qubit count. It is where the control electronics live.
The wiring problem this is aimed at
Every qubit on a chip needs a control line carrying a precisely timed microwave or voltage pulse, and in the conventional architecture each of those lines runs from a room-temperature instrument, through a dilution refrigerator's thermal stages, down to the chip at millikelvin temperatures. That works for tens of qubits. It becomes a physical bottleneck well before thousands, since each added qubit needs its own cable run, and each cable is a path for heat to leak into the coldest part of the fridge, the same scaling wall silicon and superconducting roadmaps both eventually hit.
What HRL put inside the cryostat instead
HRL's answer is a custom cryogenic CMOS control chip, built on a standard 130-nanometer RF-CMOS process, sitting inside the cryostat at 4 Kelvin and generating the control waveforms locally rather than piping them in from room temperature. The chip integrates roughly 70 million transistors and draws under 3.5 watts, a power budget deliberately kept low since a cryostat removes only so much heat before the qubits themselves warm past their operating point. A 296-channel superconducting niobium ribbon cable carries 150 time-varying control signals from the 4 Kelvin stage down to the qubits at 150 millikelvin, adding less than 10 microwatts of thermal load along the way, the figure that makes the whole architecture workable rather than a clever detail on its own.
The performance numbers
Single-qubit gate errors came in at 1.7×10⁻⁴ and two-qubit CNOT errors at 3.5×10⁻³, both in range for a research-stage device rather than a production system. A distance-5 repetition code, a basic form of quantum error correction, achieved 4.7x error suppression, and a two-logical-qubit state reached 95% fidelity. None of these numbers beat the best results from superconducting or trapped-ion platforms running far more qubits. The point of this paper is not qubit count or fidelity records. It is proving the autonomous-control architecture works at all on real hardware.
Why "manufacturing blueprint" is the right frame
HRL describes the result as a manufacturing blueprint because both halves of the system, the qubit chip and the cryo-CMOS controller, are built on standard commercial semiconductor process lines rather than exotic one-off fabrication. That distinction matters for the same reason it mattered in IonQ's SkyWater acquisition: a component manufactured on an existing commercial line scales differently than one that needs a custom, low-volume fab. Silicon spin qubits already inherit a manufacturing advantage from decades of CMOS process development. This result extends that advantage to the control electronics sitting next to the qubits, not only the qubits themselves.
What to watch next
Whether HRL or another silicon group scales this integrated-control approach past 18 qubits while holding the thermal budget and gate fidelities in the same range, since the wiring bottleneck this architecture targets only becomes a real constraint once qubit counts climb into the hundreds. An 18-qubit demonstration proves the concept works. It does not yet prove it scales, which is the harder and more relevant question for whether silicon closes the gap with superconducting and trapped-ion platforms on qubit count.