A quantum circuit describes an algorithm in a convenient gate language. Quantum hardware supports a smaller native gate set, fixed qubit connections, timing rules, and calibrated operations. Transpilation converts the first description into the second.
A transpiler preserves intended computation while changing representation for execution on a selected backend.
What a transpiler must solve
A typical pipeline handles five tasks:
- Choose physical qubits for logical circuit wires.
- Replace abstract gates with native operations.
- Add routing operations for missing connections.
- Optimize redundant or expensive gate sequences.
- Schedule operations around timing and hardware constraints.
The output depends on backend, compiler settings, optimization level, calibration data, and circuit structure.
Abstract gates versus native gates
A circuit might use H, T, controlled rotations, and arbitrary-angle gates. A processor might expose calibrated pulses or a native instruction set built from echoed cross-resonance, controlled-Z, single-qubit rotations, or trapped-ion entangling gates.
The transpiler decomposes abstract operations into supported primitives. A single high-level gate might become several native gates. Each extra operation adds duration, calibration dependence, and possible error.
Native gate choice also affects error. Two mathematically equivalent decompositions might have different measured fidelity on one backend.
Layout maps logical to physical qubits
Logical qubit 0 in source code does not guarantee physical qubit 0 on a device. Layout chooses a placement based on coupling, gate quality, calibration, and circuit interaction patterns.
A good layout places frequently interacting logical qubits close together. A poor layout forces extra movement and increases depth.
Review the final layout when a result looks worse than simulation. A circuit sometimes uses a high-error physical region or a placement with heavy routing.
Routing adds SWAP gates
Hardware connectivity is often limited. If a circuit asks for a two-qubit operation between nonadjacent qubits, the compiler moves quantum states with SWAP operations or selects a different decomposition.
A SWAP usually costs several native two-qubit gates. Routing therefore affects:
- Two-qubit gate count.
- Circuit depth.
- Total execution time.
- Error accumulation.
- Number of idle periods.
A logical circuit with ten two-qubit gates might produce dozens after routing. Record both pre-routing and post-routing counts.
Optimization passes
Compiler passes remove adjacent inverse gates, combine rotations, cancel repeated patterns, and rewrite operations for the target gate set. Some passes search for lower-depth alternatives. Others preserve structure to support pulse-level scheduling or error mitigation.
Higher optimization levels often take longer to compile. A higher level also does not guarantee better hardware results. Test several settings against the same backend and measure depth, gate count, fidelity, and total runtime.
Scheduling and idle time
Two gates sometimes share a circuit layer in an abstract diagram but require different durations on hardware. Scheduling aligns operations, inserts delays, and respects measurement and reset timing.
Idle qubits accumulate decoherence. A schedule with lower gate count might still perform worse if one qubit waits for a long operation elsewhere. Dynamical decoupling or pulse shaping sometimes fills idle windows, though added pulses also carry error and calibration cost.
Transpilation versus optimization
Transpilation means backend mapping. Optimization means improving a representation while preserving behavior. A compiler usually performs both, but the goals differ.
A circuit with fewer gates is not always faster. A native two-qubit gate might replace several abstract operations. Parallel operations might reduce depth while leaving total gate count unchanged. Compare all three: gate count, depth, and wall-clock duration.
What to record
Save the following with every hardware result:
- Backend name and version.
- Calibration timestamp.
- Initial circuit depth and gate counts.
- Final depth and native gate counts.
- Physical-qubit layout.
- Routing method and SWAP count.
- Optimization settings.
- Scheduling and dynamical-decoupling settings.
- Shot count, mitigation, and job identifier.
Without this record, a later run might execute a different circuit while appearing to repeat the same experiment.
A practical workflow
Start with a local simulator and the abstract circuit. Select a real backend only after the circuit produces the expected distribution. Transpile once for each candidate backend, inspect the output, and compare routing overhead.
Prefer a device region with good two-qubit calibration when the provider exposes such data. Keep the circuit shallow, reduce unnecessary measurements, and avoid repeated transpilation inside an optimizer unless layout changes are required.
Use the Qiskit guide, IBM free-tier guide, and randomized benchmarking guide for practical follow-up.