Qarakal Quantum Ltd., an Israeli quantum startup, published research on arXiv and launched an architecture called Pangaea on August 5, 2026. The core claim is specific and checkable in principle: in fault-tolerance simulations targeting 50 logical qubits, Pangaea matched the logical error rates of standard planar surface-code architectures while using roughly ten times fewer physical qubits. That is the kind of number that, if it survives independent scrutiny, would matter more than most hardware announcements this year, because qubit overhead is the single biggest obstacle between today's noisy processors and a fault-tolerant machine.
The problem Pangaea is aimed at
Standard 2D surface-code error correction scales physical qubit count roughly as the square of the code distance, written O(d²) per logical qubit, where d determines how well the code suppresses errors. That quadratic relationship is why credible fault-tolerant roadmaps talk about needing physical qubit counts in the hundreds of thousands to millions: the error suppression you need for useful algorithms requires a large d, and the qubit cost of a large d compounds fast under a 2D layout.
How the architecture gets around it
Pangaea is a modular, three-dimensional superconducting design that arranges specialized code patches, some running surface codes, some running color codes, as separate physical blocks rather than one flat 2D grid. The connective piece is what Qarakal calls a quantum bus: an auxiliary gauge-code strip that mediates operations between physically separated code patches by reconstructing multi-qubit joint Pauli operators, without needing the patches to sit directly adjacent to each other. That is the mechanism behind the qubit savings. Qarakal describes the resulting scaling for multi-qubit interactions as O(dNL) physical qubits for N logical qubits at distance d, versus O(d²NL) for a standard 2D layout, which is the difference between linear and quadratic growth in d. The architecture also includes a native 15-to-1 magic-state distillation module and measurement-based fault-tolerant CNOT primitives, both aimed at the same overhead problem from the operations side rather than the layout side.
What "10x" rests on
The tenfold figure comes from Qarakal's own fault-tolerance simulations, not from a physical device running the architecture, and not from an independent group reproducing the result. Simulated overhead claims in error correction have a mixed track record: some hold up when built, some run into wiring density, control electronics, or cross-talk problems that a simulation does not model well. Qarakal's design does address the wiring question directly by claiming reduced wiring density and control electronics overhead compared to a flat 2D chip, which is a real consideration for a 3D layout, but that claim is also simulation-stage, not hardware-verified.
Why this is worth tracking anyway
Every credible path to a useful fault-tolerant quantum computer runs through cutting qubit overhead, which is why IBM's move toward qLDPC-style codes, Quantinuum's trapped-ion connectivity advantage, and now Qarakal's 3D modular approach are all answers to the same underlying question from different hardware angles. Our piece on Quantinuum's Helios encoding ratio covers why the physical-to-logical qubit ratio, not raw qubit count, is the number that indicates real progress, and Pangaea's claim is trying to move that same ratio with a different technique.
What to watch next
The test for Pangaea is whether Qarakal, or an independent lab, builds a physical device that reproduces the simulated overhead reduction rather than the architecture staying a paper design. A 3D superconducting layout also raises fabrication and cooling questions that a 2D chip does not face, and how Qarakal handles those in practice is the next thing worth checking, not the arXiv numbers alone.